1. Technical Field
The present invention relates to a technology for decoding compress-encoded moving image data, and especially to a technology for improving memory access efficiency when a processing unit having a cache mechanism processes signals.
2. Background Art
As a method for compressing the data amount of moving image data for recording or transmission thereof, an international standard called MPEG (Moving Picture coding Experts Group) is widely prevalent. The MPEG family includes MPEG-1, MPEG-2, and MPEG-4. MPEG-1 has been widespread as a moving image encoding standard for CD (Compact Disc). MPEG-2 supports digital TV and DVD (Digital Versatile Disc). MPEG-4 adopts a lower bit rate on the assumption that it is used in the Internet or mobile communications. Also, in recent years, H.264/AVC (Advanced Video Coding) has been established for further improvement of the compression rate, and machines using this are increasing.
To decode image data having been compressed in compliance with such an MPEG standard, an enormous amount of calculation is required. For this reason, it was typical for machines conforming to an MPEG of earlier days to use a dedicated hardware device to decode MPEG-compressed data while maintaining the real-timeness. However, due to development of the technology of calculators in recent years, it has become possible to decode in real time only by software, without using a dedicated hardware device. As the dedicated hardware has become unnecessary, more varieties of machines have become possible to use MPEG data, and it is expected that the tendency will increase.
The decoding algorithm of MPEG is composed of four processes: a variable length encoding/decoding process called VLD (Variable Length Decoding); an inverse quantization process; an inverse DCT (Discrete Cosine Transform) process; and a motion compensation process. The above-mentioned MPEG-1, MPEG-2, MPEG-4, and H.264/AVC use almost the same algorithm with sight differences.
A system for decoding MPEG data generally includes an external storage device such as HDD or CD/DVD, a main memory, a CPU, and a display device. The external storage device stores MPEG data. The CPU reads out the MPEG data from the external storage device, and stores the read-out MPEG data into the main memory temporarily. The CPU decodes the MPEG data stored in the main memory by using a decoding process program that operates at the CPU, and stores image data resulted from the decoding into the main memory again. The CPU then reads out the image data from the main memory, performs a format conversion onto the image data so that the display device can display the image data, and transfers the conversion result to the display device. The display device displays images of the received image data.
FIG. 14 shows picture (namely, image data) arrangement when pictures are decoded by an MPEG method. The MPEG defines three types of pictures: I-picture being a picture that can be decoded only from information contained in the picture itself, without performing the motion compensation; P-picture that requires a motion compensation process in which a predictive decoding process of the target picture is performed using backward picture information; and B-picture that requires a predictive decoding process of the target picture using both forward and backward picture information.
FIG. 14A shows an arrangement of pictures stored in the external storage device. The number assigned to each picture indicates its place in the arrangement. The picture type of each picture is indicated below each picture. In FIG. 14A, picture 1 is an I-picture, and thus it can be decoded without information of other pictures. Pictures 2 and 3 are B-pictures, and thus need to be decoded using information of both pictures 1 and 4. B-pictures are not used in predictive processes for the other pictures. Picture 4 is a P-picture, and thus needs to be decoded using information of picture 1. Similarly, pictures 5 and 6 are decoded using information of pictures 4 and 7, and picture 7 is decoded using information of picture 4.
FIG. 14B shows a decoding process order in accordance with the picture types and the decoding order described above. In the actual decoding process, first, picture 1 of I-picture is decoded. Next, picture 4 of P-picture is decoded using the image data of decoded picture 1. Then, pictures 2 and 3 of B-pictures are decoded in sequence using the image data of decoded pictures 1 and 4. Picture 6 and after are decoded in a similar manner. Namely, after a P-picture is decoded, a B-picture is decoded. The decoding order should be the same as the compression process order defined in MPEG.
FIG. 14C shows an order in which images, having been obtained by the decoding, are displayed.
In the MPEG decoding process, access to the main memory occur frequently. Typically, in the above-described system, the CPU is provided with a cache memory in order to reduce the access load to the main memory. The cache memory has less capacity than the main memory, which is located outside the CPU and connected with the CPU, but is designed to be accessible at an extremely high speed.
For example, to decode the picture 4 of P-picture shown in FIG. 14B, the CPU obtains, from the picture 1 of I-picture, macro blocks (typically four macro blocks) that are to be referred to in the decoding process, using a motion vector that is included in the decoding target macro block to be decoded, and stores the obtained macro blocks into the cache memory. The CPU then decodes the decoding target macro block using the stored macro blocks. The CPU then obtains the next decoding target macro block, obtains, from the picture 1 of I-picture, macro blocks (typically four macro blocks) that are to be referred to in the decoding process, using a motion vector that is included in the obtained decoding target macro block, and stores the obtained macro blocks into the cache memory. The CPU then decodes the decoding target macro block using the stored macro blocks. At this time, the four macro blocks that had been stored in the decoding of the first decoding target macro block have been deleted from the cache memory. The CPU repeats the operation until all macro blocks of the P-picture have been decoded. After the P-picture is decode, the B-picture is decoded. In this case, basically the CPU repeats the above-described operation, but the pictures to be referred to are an I-picture and a P-picture.
In many cases, the macro blocks that are referred to in the decoding of the P- or B-picture are used only once in the decoding of one picture. Also, as the case now stands, according to a typical method, the MPEG data is processed one picture by one picture in the decoding thereof. Therefore, the reference picture data having been read into the cache memory is rarely accessed continuously and is discarded without being re-used. That is to say, the cache memory is used with extremely low efficiency.
According to the method of decoding the MPEG data, since it is impossible to store, into the cache memory, all macro blocks (the entire reference-target picture that has been decoded) that should be referred to in the motion compensation process, same pieces of data (macro blocks to be referred to) need to be read out from the main memory a lot of times. This deteriorates the performance of the decoding process.
As a technology aimed to solve the above-described problem, Patent Document 1 identified below discloses a method in which data stored in the cache memory is used efficiently to prevent reduction in the speed of the decoding process, making use of a property that B-pictures arranged in succession have similarity. According to this method, when a picture to be decoded is a B-picture and the next picture is also a B-picture, a decoding process for one macro block of the first picture and a decoding process for one macro block of the second picture are performed alternately such that the decoding processes for the adjacent two pictures are performed at the same time (instead of one macro block for each picture, a predetermined number of macro blocks for each picture may be decoded in the alternate decoding). That is to say, in Patent Document 1, when adjacent two pictures are both B-pictures, the decoding processes for the two pictures are performed alternately in unit of one macro block or a plurality of macro blocks. With this method, it is possible to reduce the probability of occurrence of a cache error during the motion compensation process since decoding processes for macro blocks located at a same position of the adjacent pictures are performed continuously. The method is making use of the property that motion compensation processes for macro blocks located at a same position of the adjacent pictures tend to use an area (macro block) in a reference picture that is located near the position of the macro blocks.                Patent Document 1: Japanese Patent No. 3322233, Description        Non-Patent Document 1: ITU-T Rec. H.264 ISO/IEC 14496-10 AVC Joint Final Committee Draft of Joint Video Specification (2002 Aug. 10) (page 54, 8.3.6.3 Default index orders, page 56, 8.3.6.4 Changing the default index orders)        